Alphacore’s design is an application specific integrated circuit (ASIC) that provides significant SWAP (size, weight and power) reduction as compared to the existing board-level systems that use COTS ADCs and FPGAs. The ASIC will have a 2 GS/S (gigasamples per second), 12-bit, <40mW, radiation hard ADC and a 256-channel back-end digital signal processing (DSP) block consuming <100mW.
It will be developed in a small-geometry CMOS silicon on insulator (SOI) technology (28nm) that is inherently tolerant to relatively high total ionizing dose (at least 500krad(Si) can be expected), and has better immunity to single event effects than bulk CMOS processes (no latchup, better upset rate due to isolation).
This receiver backend greatly benefits future NASA missions that need systems to detect interference in different bands of frequencies such as radiometer microwave sensors and advanced RF communications applications
